Electronic design automation (EDA) is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that chip designers use to design and analyse entire semiconductor chips. A process design kit (PDK) is a set of files used within the semiconductor industry to model devices such as transistors in the layout of a chip and are used with a suitable design software tool such as Cadence. In order to efficiently design complex circuits, each device of the PDK is generated by a parameterized cell (pcell) that automatically builds the different required shapes and layers. The pcell guarantees the integrity of the layout, and its compliance to manufacturing rules. When designing a product, the engineers may have to “flatten” a pcell, which breaks the built-in relationship between shapes and levels of the original device. In other words, when the device is flattened, the engineers can freely move shapes with respect to each other that may result in an improper device behaviour.
In a PDK, the proper electrical behaviour of each device is guaranteed by a series of ground rules that fix the relative position (spacing, width, and the like) of each shape that belongs to a specific device. The rules are coded in a validation tool referenced as Design Rule Checker (DRC), provided by several EDA vendors such as Cadence, Mentor Graphics and Synopsys. For most devices, simple DRC checks are sufficient to verify the proper integrity of the device. As an example, the checking of channel width and length of low voltage FETs is sufficient to guarantee a device behaviour consistent with that of the model. For advanced technology nodes and analogue, RF and power technologies more complex structures such as bipolar transistors, or high voltage FETs are widely used in such advanced products.
More complex rules have to be implemented to validate these more complex structures that involve more shapes, more design layers and larger circuits in the layout. In turn, this imposes new constraints on the validation tools, both in terms of runtime and capabilities. The complex rules are often referred as “element rules”, since they relate to a single device also known as an element, and form part of a new class of DRC checks referenced as ERC (Electrical Rule Checks). Presently, existing DRC/ERC algorithms and production tools, as well as limited time used to develop and code complex rules, resulting possible errors in the validation of large and complex designs.